diff --git a/buildarmpit b/buildarmpit
index be98597..ec4c8c9 100755
--- a/buildarmpit
+++ b/buildarmpit
@@ -39,6 +39,7 @@
 # 	./buildarmpit 060 LM_3Sxxxx  TI_EvalBot		 // TI           Evalbot LM3S9B92
 # 	./buildarmpit 060 LPC_1300   LPC_P1343		 // Olimex       LPC-P1343
 # 	./buildarmpit 060 LPC_1700   Blueboard_1768	 // NGX          Blueboard LPC1768-H
+#       ./buildarmpit 060 LPC_1700   mbed_NXP_LPC1768    // NXP          mbed NXP LPC1768
 # 	./buildarmpit 060 STM32F1    STM32_DT_Board	 // InSem/Lodin  STM32-DOT-BOARD
 # 	./buildarmpit 060 STM32F1    STM32_Fractal	 // Fractal MCU32-1.12 Board
 # 	./buildarmpit 060 STM32F1    STM32_H103		 // Olimex       STM32-H103
diff --git a/mcu_specific/LPC_1700/init_io_code.s b/mcu_specific/LPC_1700/init_io_code.s
index 9aa840a..5d798f5 100644
--- a/mcu_specific/LPC_1700/init_io_code.s
+++ b/mcu_specific/LPC_1700/init_io_code.s
@@ -331,6 +331,15 @@ FlashInitCheck: @ return status of flash init enable/override gpio pin (P3.26) i
 	set	pc,  lnk
 .endif
 
+.ifdef mbed_NXP_LPC1768
+_func_
+FlashInitCheck: @ return status of flash init enable/override gpio pin (P3.26) in rva
+		@ pin low = boot override
+	ldr	rva, =io3_base		@ rva <- address of gpio 3 base register
+	ldr	rva, [rva, #io_state]	@ rva <- values of all P3.X
+	and	rva, rva, #0x04000000	@ rva <- status of P3.26 only (return value)
+	set	pc,  lnk
+.endif
 	
 @---------------------------------------------------------------------------------------
 @
diff --git a/mcu_specific/LPC_1700/init_io_data.s b/mcu_specific/LPC_1700/init_io_data.s
index 857849b..45a6863 100644
--- a/mcu_specific/LPC_1700/init_io_data.s
+++ b/mcu_specific/LPC_1700/init_io_data.s
@@ -120,4 +120,20 @@ lib_sectors:	@ lib shares on-chip file flash
 
 
 
+.ifdef mbed_NXP_LPC1768
+@
+@ Note:	 on some LPC1768 hardware (week 11 to 34, 2010) the sector starting at 0x70000 cannot be written.
+@
+.balign	4
+flashsectors:	@ 16 x 4KB, 14 x 32KB FLASH sectors of LPC1768
+lib_sectors:	@ lib shares on-chip file flash
+.word	0x00000, 0x01000, 0x02000, 0x03000, 0x04000, 0x05000, 0x06000, 0x07000
+.word	0x08000, 0x09000, 0x0A000, 0x0B000, 0x0C000, 0x0D000, 0x0E000, 0x0F000
+.word	0x10000, 0x18000, 0x20000, 0x28000, 0x30000, 0x38000, 0x40000, 0x48000
+.word	0x50000, 0x58000, 0x60000, 0x68000, 0x70000, 0x78000, 0x80000, 0x0FFFFFFC
+.endif	@ .ifdef mbed_NXP_LPC1768
+
+
+
+
 
diff --git a/mcu_specific/LPC_1700/mbed_NXP_LPC1768/board.h b/mcu_specific/LPC_1700/mbed_NXP_LPC1768/board.h
new file mode 100644
index 0000000..50cd7eb
--- /dev/null
+++ b/mcu_specific/LPC_1700/mbed_NXP_LPC1768/board.h
@@ -0,0 +1,90 @@
+/*------------------------------------------------------------------------------
+@
+@  ARMPIT SCHEME Version 060
+@
+@  ARMPIT SCHEME is distributed under The MIT License.
+
+@  Copyright (c) 2006-2013 Hubert Montas
+
+@ Permission is hereby granted, free of charge, to any person obtaining
+@ a copy of this software and associated documentation files (the "Software"),
+@ to deal in the Software without restriction, including without limitation
+@ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+@ and/or sell copies of the Software, and to permit persons to whom the
+@ Software is furnished to do so, subject to the following conditions:
+@
+@ The above copyright notice and this permission notice shall be included
+@ in all copies or substantial portions of the Software.
+@
+@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+@ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+@ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+@ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+@ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+@ OTHER DEALINGS IN THE SOFTWARE.
+@
+@-----------------------------------------------------------------------------*/
+
+@-------10--------20--------30--------40--------50--------60--------70--------80
+
+/* =======  BOARD =========== */
+mbed_NXP_LPC1768 = 1		@ NXP mbed LPC1768
+
+/* ======= OPTIONS ========== */
+native_usb	= 1		@ comment out to exclude usb support
+onboard_SDFT	= 1		@ comment out to exclude SD card file subsystem
+enable_MPU	= 1		@ comment this line out to not use the MPU
+
+/* ===== CONFIGURATION ====== */
+@ --------- LEDs -----------
+LEDPINSEL	= PINSEL3	@ board LED control is on PINSEL3 
+LEDIO		= io1_base	@ board LED on/off pins are on IO1PINs
+GRNLED		= 1 << 18 	@ aliased [ LED are on pins 18,20,21,23 ]
+REDLED		= 1 << 20 	@ aliased
+YELLED		= 1 << 21       @ P1.29
+LED4		= 0x2009C020    @ P1.29
+@ --------- SD card ---------
+sd_is_on_spi	= 1		@ SD card uses SPI interface
+sd_spi		= spi0_base	@ SD card is on SPI0 (legacy SPI)
+sd_spi_gpio	= io0_base	@ SD card SPI0 gpio0 P015,17,18=SCK0,MISO0,MOSI0
+sd_cs_gpio	= io0_base	@ SD card chip-select is on gpio0
+sd_cs		= 1 << 16	@ SD card chip-select P0.16 (the 16 in 1 << 16)
+@ --------- FREQs -----------
+CLOCK_FREQ	= 0x017700	@ 96000 kHz = clock frequency (96 MHz)
+PLL_PM_parms	= 0x0B		@ 12 MHz Xtal PLL div 1, multiplier 12 -> 288MHZ
+UART0_DIV_L	= 0x38		@ lower byte of div for 9600 baud, pclk = 48MHz
+UART0_DIV_H	= 0x01		@ upper byte of div for 9600 baud, pclk = 48MHz
+@ --------- RAM ------------
+RAMBOTTOM	= 0x10000000	@ Main on-chip RAM
+RAMTOP		= 0x10008000	@ LPC 1768 (32 kB)
+@ --------- BUFFERS --------
+BUFFER_START	= 0x2007C000+4	@ AHB RAM Bank 0, 16KB, 0x2007C000 to 0x2007FFFF
+RBF_size	= 0x1000	@ READBUFFER  size for tag as bytevector (4KB)
+WBF_size	= 0x0C00	@ WRITEBUFFER size for tag as bytevector (3KB)
+I2C0ADR		= i2c0_base + i2c_address
+@ --------- FLASH ----------
+@ Note: some LPC1768 hardware revisions have the flash sector at 0x70000 not
+@	write-able even though IAP does not return an error (0x78000 remains
+@	write-able though).
+@       This is undocumented but discussed in electronix.ru forums (Dec. 6,
+@	2010 to Mar. 3, 2011) and apparently confirmed by NXP (chips from
+@	week 11 to 34 of 2010, possibly marked: rescreen).
+@
+@       Select F_END_PAGE and LIB_TOP_PAGE accordingly below.
+@
+F_START_PAGE	= 0x00010000	@ address of 1st page of FLASH (for files)
+@F_END_PAGE	= 0x00078000	@ page after last page of FLASH used for files
+F_END_PAGE	= 0x00068000	@ 0x70000 not accessible on this NXP mcu rev
+F_PAGE_SIZE	= 256		@ size of pages used for files
+SHARED_LIB_FILE	= 1		@ library and file space share on-chip flash
+LIB_BOTTOM_PAGE	= 0x00020000	@ 128KB into flash, after 2x32KB file pages+code
+@LIB_TOP_PAGE	= 0x00080000	@ after last flash page
+LIB_TOP_PAGE	= 0x00070000	@ adjusted: 0x70000 no-access on this NXP mcu
+
+@-------10--------20--------30--------40--------50--------60--------70--------80
+
+
+
+
+
