A Scheme Interpreter for ARM Microcontrollers:
ChangeLog for Version 00.0137
Changes from version 00.0098:
Support was added for 5 new boards:
Future Designs LCDDemo-LPC2158,
Luminary Micro Stellaris LM3S1968 Evaluation Board,
Olimex CS-EP9302, LPC-H2888 and STM32-H103.
These boards are based on NXP LPC2158 (ARM7TDMI), Luminary Micro Stellaris LM3S1968 (Cortex-M3),
Cirrus EP9302 (ARM920T), NXP LPC2888 (ARM7TDMI) and ST STM32 (Cortex-M3) MCUs, respectively.
This support includes cache activation on the EP9302 and LPC2888.
It does not yet include USB and I2C functionality and does not yet include the EP9302's Maverick Crunch
Support for Cortex-M3 cores (ARMv7M architecture) has been added (in addition to the existing
support for the ARMv4T architecture of ARM7TDMI and ARM920T cores in version 00.0098).
The source code has been reworked to be compatible with the Cortex-M3 Thumb-2 instruction set
and automatic register stacking on interrupt.
This involved the addition of IT (if-then) instructions and also
modifying the mapping of registers between scheme and raw values compared to that used in prior versions.
Additionally, the obarray has been moved to the global scheme vector, freeing a register named rvc (raw
value c, aka r12).
Memory allocation functions (zmaloc, save, cons, list) have been reworked to be transactional.
An interrupt during memory allocation causes the allocation to be restarted when the interrupted
context is resumed (possibly after another thread relinquishes control).
This improves interrupt latency by reducing the code sections where interrupts need to be disabled
and also reduces overall code size.
Interrupts that perform memory allocation check first if a gc was in progress and resume it
prior to performing said allocation, if needed.
Additionally, memory allocation is now aligned to double words (8 bytes) to support mark-and-sweep
garbage collection (see below).
A mark-and-sweep garbage collector has been added as an option (the default remains stop-and-copy).
It allows significantly more of the MCU's RAM to be used for the heap.
It is however currently visibly much slower than stop-and-copy.
It is not compatible with the 2 MCUs with smallest RAM (Tiny2131 and LPC-H2103) where the
inactive stop-and-copy heap space is used in file writing operations.
File operations have been made thread-safe by using a lock for serialization of critical
code segments on the ARMv4T architecture.
This is not yet implemented on Cortex-M3 MCUs and has been removed from the AT91SAM7 because
it unexpectedly breaks on this MCU.
The function (unlock) has been added to unlock the file system when a file operation errors-out
Register addresses used in (read ...) and (write ...) operations are now specified with a
4-bit right shift (one hexadecimal digit).
For example, where one used (read #xE0000000 #x0C) in version 00.0098, one would now use
(read #x0E000000 #x0C) in version 00.0137.
This makes it possible to address the full memory range of the MCUs despite Armpit Scheme's
30-bit internal representation of integers.
Among other things, it makes it possible to turn the power to the ADC on and off on the STR711.
The macros quasiquote, and, or, let, let*, letrec, do, case and cond are now implemented as
assembly source code rather than dynamically-expanded scheme macros.
They are more compact and execute much faster.
USB issues on the LPC-H2148 have been corrected.
This includes enumeration on Mac OSX and the (former) inability to reconfigure pinsel1 pins when USB
On the LPC-H2214, the file system is now stored on the external FLASH chip and a bug
in the function (length ...) has been corrected.
Functionality that was present in version 00.0098 but not yet implemented in 00.0137,
along with known bugs and issues in this version, are documented in the Bugs and "Features" page.
Program examples have been developed to illustrate these changes where they lead to code that differs
from that of previous versions and/or to indicate on which boards these examples have run.
Last updated June 17, 2008